Despite the popularity of the ESP8266, I have yet to see a detailed datasheet published. Nava Whiteford, on his blog, has links to a summary datasheet and a Cadence tensilica core that the chip is based on. None of this provides any details on how the memory controller pages in data from the SPI flash, nor the speed of the communications. About all that is clear from the datasheet and chip markings is that it uses a quad-SPI serial flash chip.
I decided to find out the performance of the SPI flash, as well as get an idea of what the cache line fill size of the chip is. By looking at the pin-out of the flash chip, I determined that pin 6 is the clock. After some probing and playing with the settings on my scope, I captured the clock burst shown above.
Based on the 500ns horizontal scale, the clock burst lasts a little more than 2uS. Zooming in shows that the clock is exactly 40Mhz, or half of the ESP8266 80Mhz clock and have of the maximum 80Mhz speed rating of the SPI flash. Given the burst lasted a little more than 2uS, the total number of clock pulses is in the range of 85-90. Accounting for the overhead of commands to enable quad SPI mode and address setup, it seems the burst corresponds to reading 32 bytes from the flash, and therefore the cache line size is likely 32 bytes.
The clock signal is clean, and with a rise + fall time of 11.1ns, could be increased to 90Mhz without significant distortion or attenuation. With documentation on the registers to change the clock speed to 160Mhz, the ESP8266 can be run at double speed without overclocking the SPI flash.