Doing more with pin-limited MCUs seems to be a popular challenge, as my post nrf24l01+ control with 3 ATtiny85 pins is by far the most popular on my blog. A couple months ago I had an idea of how to multiplex the MOSI and MISO pins, and got around to working on it over the past couple weeks. The result is that I was able to control a nRF24l01+ module using just two pins on an ATtiny13a. I also simplified my design for multiplexing the SCK and CSN lines so it uses just a resistor and capacitor. Here's the circuit:
Starting with the top of the circuit, MOMI represents the AVR pin used for both input and output. The circuit is simply a direct connection to the slave's MOSI (data in) pin, and a resistor to the MISO. Since this is not a standard SPI configuration, I've written some bit-bang SPI code that works with the multiplexing circuit. To read the data, the MOMI pin is simply set to input. Before bringing SCK high, MOMI is set to output and the pin is set high or low according to the current data bit. The 4.7k resistor keeps the slave from shorting out the output from the AVR if the AVR outputs high, or vice-verse.
Looking at the SCK/CSN multiplexing part of the circuit, I've removed the diode that was in the original version. The purpose of the diode was to discharge the capacitor during the low portion of the SCK clock cycles, so the voltage on the CSN pin wouldn't move up in accordance with the typical 50% duty cycle of the SPI clock. My bit-bang duplex SPI code is written so the clock duty cycle is less than 25%, keeping CSN from going high while data is being transmitted. The values for C1 and R1 are not critical and are just based on what was within reach when I built the circuit; in fact I'd recommend lower values. 470Ohms * .22uF gives an RC time constant of 103uS, meaning SCK needs to be held low for >103uS for C1 to discharge enough for CSN to go low. Something like a 220Ohm resistor and .1uF capacitor would reduce the delay required for CSN to go low to around 25uS.
The R2 is far more important. The first value I tried was 1.5K, and after fixing a couple minor software bugs, it seemed to be working OK. When I looked at the signals on my scope, I saw a problem:
The yellow trace shows the voltage level detected on the MOMI pin at the AVR. Each successive high bit was a bit lower voltage, so after more than a few bytes of data, all the bits would likely be read as zero. I suspect this has something to do with the internal capacitance of the output drivers on the nRF module, as well as it's somewhat weak drive strength, documented in the datasheet at table 13. A 4.7K resistor seems to be optimal, though anything from 3.3K to 6.8K should work.
Software
Here is the AVR code for the time-division duplexed SPI:
uint8_t spi_byte(uint8_t dataout)
{
uint8_t datain, bits = 8;
do{
datain <<= 1;
if(SPI_PIN & (1<<SPI_MOMI)) datain++;
sbi (SPI_DDR, SPI_MOMI); // output mode
if (dataout & 0x80) sbi (SPI_PORT, SPI_MOMI);
SPI_PIN = (1<<SPI_SCK);
cbi (SPI_DDR, SPI_MOMI); // input mode
SPI_PIN = (1<<SPI_SCK); // toggle SCK
cbi (SPI_PORT, SPI_MOMI);
dataout <<= 1;
}while(--bits);
return datain;
}
I also wrote unidirectional spi_in and spi_out functions that work with the multiplexed MOSI/MISO. Besides being faster than spi_byte, these functions work with the SE8R01 modules that have inconsistent drive strength on their MISO line.
The functions are in halfduplexspi.h, and I also wrote spitest.c, which will print the value of registers 15 through 0. Here's a screen capture of the output from spitest.c:
