A look at the USBasp schematic shows USB D- and D+ connected to PB0 and PB1. With the UART output rate of 6mbps and a 12Mhz CPU clock rate, a full 10-bit frame takes 20 cycles. To take 4 2-bit samples every 20cycles requires taking a sample and packing those two bits into a byte every 5 cycles. Single-cycle timing is very difficult to do in C, so I wrote the code in AVR assembler.
| capture2: | 
| in sample, PINB | 
| out UDR, tmp | 
| andi sample, 0x03 | 
| lsl sample | 
| lsl sample | 
| in tmp, PINB | 
| andi tmp, 0x03 | 
| or sample, tmp | 
| lsl sample | 
| lsl sample | 
| in tmp, PINB | 
| andi tmp, 0x03 | 
| or sample, tmp | 
| lsl sample | 
| lsl sample | 
| in tmp, PINB | 
| andi tmp, 0x03 | 
| or tmp, sample | 
| rjmp capture2 | 
To be able to view the captured data, I like OLS. It will read a simple text-based input file, which I wrote a small perl progam to output. It takes a single argument, which is the serial port to read from. Under windows I had problems getting perl to open high com ports (i.e. com10 or above), so I used the device manager advanced properties to change the port number to com2. I also wrote a similar program for the 8-bit mode. One second of samples will be recorded, although there is no technical limit to how long can be recorded.
Here's a portion of a screen shot of OLS showing a USB setup packet followed by 2 re-transmits after ~10us without receiving an ACK:
It's not as fast as the Logic Shrimp, but considering unlimited sampling length and the required hardware is a USB-TTL adapter that costs barely over $1 and a ~$3 USBasp that many people already have, now anyone can afford a basic logic analyzer.

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